Integrated circuits often communicate data signals “synchronously,” which means that the communicating circuits time the transmission and receipt of the data to a common reference. In source-synchronous systems the timing reference is sourced by the same circuit that transmits the data. Being from the same source, the data and timing-reference signals are developed by the same circuit and traverse similar communication channels, and consequently experience similar phase distortion due to, e.g., transmission delays, supply-voltage noise, and temperature fluctuations. Distortion that tends to advance or retard the phase of the data signals will likewise advance or retard the phase of the associated timing reference, for example, so the similar phase errors cancel at the receiver.
Double Data Rate (DDR) memory interfaces exemplify high performance, source-synchronous channels. DDR devices convey data signals with a concomitant strobe signal. The strobe signal is like a clock signal that is turned off when there is no data to sample. In the case of DDR devices, a strobe signal from a memory device is activated when data is read from the device, and that strobe is used by a receiving memory controller to recover the data. For memory writes, the memory controller asserts a strobe signal concomitant with the data to be written. The data strobe timing pattern includes a preamble that precedes the data and allows for the receiving device to enable the circuitry necessary to capture the imminent data, a toggling portion that includes signal transitions for timing receipt of the data, and a postamble that returns the strobe line to a stable, low-power state.